As semiconductor fabrication processes continue to shrink, the evolving lithography equipment, the optical proximity correction methods, and the increasingly restrictive design rules are usually doing a good job at maintaining the desired transistor shapes and especially sizes. However, the ongoing layout scaling combined with undesirable effects such as line edge roughness is bringing several increasingly disturbing issues related to variability of transistor performance for technology nodes below 45 nm.
In particular, edges in the active layer are becoming increasingly curvilinear whenever several transistors with different channel widths are placed next to each other, and with gate lengths pushing under 30 nm and channel widths pushing under 100 nm, line edge roughness no longer averages out across the channel. Instead, it contributes to the active layer curvatures on top of optical proximity and etch bias effects.
FIG. 1A illustrates a typical integrated circuit layout portion in which three transistors having different channel widths share a common diffusion layout shape 110. The three transistors are identifiable by the polysilicon gate shapes 112, 114 and 116 representing transistors T112, T114 and T116, respectively. From left-to-right in the drawing, transistor T112 has the largest width, T114 is narrower, and T116 is narrowest. In order to define the channel widths, one longitudinal side of the diffusion layout shape 110 (the upper side 118 in the drawing) jogs inward (downward in the drawing) at longitudinal position 120 just to the left of gate shape 112, and again at longitudinal position 122 just to the left of gate shape 116. The other longitudinal side of the diffusion layout shape 110 (the lower side 124 in the drawing) jogs inward (upward in the drawing) at longitudinal position 126 just to the left of gate shape 114. Jogs are often made at longitudinal positions close to the narrower transistor channel so as to maximize the current flow through the wider transistor channel. In the diffusion layout shape 110, the jogs 120, 122 and 126 result in inner corners 128, 130 and 132, respectively, located at longitudinal positions which are close to gate shapes.
FIG. 2 illustrates features on an integrated circuit as might be printed using state-of-the-art 193 nm steppers, and a mask set generated using the shapes in FIG. 1A. It can be seen that all the rectangular corners in the layout shapes have been rounded due to diffraction effects. The three circles that have been drawn on the diagram of FIG. 2 illustrate that the rounding radius for the active/diffusion layer is of the order of 60 nm. This radius cannot be reduced significantly by optical proximity correction (OPC) techniques. In addition, it can be seen that due to the tight poly pitch, rounded corners 128, 130 and 132 extend into the transistor channels and distort the intended rectangular channel shape.
The fundamental reasons behind the rounded corners are the need to have transistors with different channel widths that can be achieved by jogs in active/diffusion layer and the inability of 193 nm lithography to squeeze such jogs in between the two poly gates. This problem is expected to get worse as poly-to-poly distance shrinks by 0.7× with each technology node. Typical poly-to-poly distances are expected to be 95 nm for 32 nm node and 65 nm at 22 nm node. Both distances are smaller than two corner rounding radii, which guarantees that channel shapes will be non-rectangular as transistor fabrication processes shrink to these nodes. Prior to now it was not clear how such channel shapes will affect transistor performance parameters, and hence circuit performance and reliability.